# Intel 指令 ## sfence ```mermaid stateDiagram-v2 W(A) --> W(B) W(B) --> W(C): sfence ``` - 保证对 A，B 的写入，在写 C 之前，先全局可见。 - 用于 serialize store/write 指令，不影响 load 指令。 > Existing formalizations of Intel-x86 treat sfence simply as a NOP, since stores are already ordered under TSO. > > *Extending Intel-x86 Consistency and Persistency* - 其他用途：与 clflushopt 结合使用 ## lfence - 避免 load 向前重排(speculative load)，用于 serialize load 指令。 ## mfence - flush store buffer - 同时避免 store-load 重排 > reads cannot pass LFENCE and MFENCE instructions > writes cannot pass SFENCE and MFENCE instructions -------- # 参考资料 - [A better x86 memory model: x86-TSO](https://www.cl.cam.ac.uk/~pes20/weakmemory/x86tso-paper.pdf) - [Extending Intel-x86 Consistency and Persistency](https://dl.acm.org/doi/pdf/10.1145/3498683) - Intel® 64 and IA-32 Architectures Software Developer’s Manual - https://stackoverflow.com/questions/54876208/size-of-store-buffers-on-intel-hardware-what-exactly-is-a-store-buffer/54880249#54880249